DESIGN AND CHARACTERIZATION OF A CMOS VLSI SELF-TIMED MULTIPLIER ARCHITECTURE BASED ON A BIT-LEVEL PIPELINED-ARRAY STRUCTURE

The authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The different ial structure SODS (switched-output differential structure) has been u sed for computation blocks and the PLCAR structure (protocol and latch ing controlled by acknowledge and request) for the interface blocks, i ntroduced in an array-based architecture. A 4 x 4-bit multiplier has b een integrated in a 1.0 mu m CMOS technology and the proposed architec ture has been compared with other asynchronous approaches, showing a c onsiderable improvement, up to 50% in terms of area, speed and power c onsumption. Compared with a synchronous approach, the main advantage o f the proposed architecture is a lower power consumption below a certa in incoming input data rate, but at the expense of area and speed.