AN 80-GBIT S MULTIPLEXER IC USING INALAS/INGAAS/INP HEMTS/

This paper describes the design and performance of an 80-Gbit/s 2:1 se lector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMT's. B y using a double-layer interconnection process with a low-dielectric i nsulator, microstrip lines were designed to make impedance-matched, hi gh-speed intercell connection of critical signal paths. The record ope rating data rate was measured on a 3-in wafer. In spite of the bandwid th limitation on the measurement setup, clear eye patterns were succes sfully observed for the first time. The obtained circuit speed improve ment from the previous result of 64 Gbit/s owes much to this high-spee d interconnection design.