CHARACTERIZATION OF BORDER TRAP GENERATION IN RAPID THERMALLY ANNEALED OXIDES DEPOSITED USING SILANE CHEMISTRY

The border trap generation under high held stressing has been characte rized in rapid thermal annealed low pressure chemical vapor deposited gate oxides. The hysteresis in high frequency capacitance-voltage curv e is used to characterize the border traps. It is shown that at least some of the border traps are not associated with trapped positive char ge. The border traps are charged and discharged through electrons tunn eling from and to the substrate. The hysteresis is independent of temp erature confirming the tunneling model. The effects of different annea ling ambients suggest that the border trap generation depends on the p hysical stress at the substrate interface, which is qualitatively meas ured using Fourier transform infrared spectroscopy. The border trap ge neration is attributed to bond breaking at the substrate interface by energetic electrons. (C) 1998 American Institute of Physics. [S0021-89 79(98)03217-4].