OVER-60-GHZ DESIGN TECHNOLOGY FOR AN SCFL DYNAMIC FREQUENCY-DIVIDER USING INP-BASED HEMTS

A toggle operation of 39-63.5 GHz without tuning has been achieved by a digital dynamic frequency divider (DFD). The DFD employs a pair of c locked inverters (CI's) with source-coupled FET logic (SCFL) and uses 0.1-mu m-gate InAlAs/InGaAs/InP high electron-mobility transistors (HE MT's) of good uniformity and high performance. On a 2-in wafer, the fr equency divider showed a maximum toggle frequency (f(tog, max)) of 59. 1 +/- 3.3 GHz and a fabrication yield of 89%. This is the highest oper ation frequency ever reported for a broad-band digital frequency divid er. Comparison of the DFD and the static frequency divider (SFD) showe d that the ratio of f(tog, max) for the DFD to that for the SFD is muc h higher than the value expected from the linear-response theory. The comparison also showed that the ratio of the measured f(tog max) for t he DFD to that for the SFD is 1.7, in contrast with the value of two e xpected from the circuit simulation, Delay-time analysis revealed that this 15% decrease of the ratio is due to the transmission delay of in terconnections and charging time for stray capacitance.