A LOW-POWER DSP CORE ARCHITECTURE FOR LOW BITRATE SPEECH CODEC

A VLSI implementation of a low-power DSP core is described, which is d edicated to the G.723.1 low bitrate speech codec. A number of sophisti cated DSP microarchitectures are devised mainly on dual multiply accum ulators, rounding and saturation mechanisms, and two-banked on-chip me mory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a f airly small increase of chip area. The proposed DSP architecture has b een integrated in the total area of 7.75 mm(2) by using a 0.35 mu m CM OS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.