POWER ESTIMATION UNDER UNCERTAIN DELAYS

While estimating glitches or spurious transitions is a challenge due t o signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output n odes of combinational Complementary Metal-Oxide-Semiconductor (CMOS) l ogic circuits considering uncertainty of gate delays. The methodology is based on the stochastic models of logic signals and the probabilist ic behavior of gate delays due to process variations, interconnect par asitics, etc. We propose a statistical technique of estimating average -case activity, which is flexible in adopting different delay models a nd variations and can be integrated with worst-case analysis into stat istical logic design process. Experimental results show that the uncer tainty of gate delays has a great impact on activity at individual nod es (more than 100%) and total power dissipation (can be overestimated up to 65%) as well.