A TECHNIQUE FOR ESTIMATING SIGNAL ACTIVITY IN LOGIC-CIRCUITS

In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic si gnal is modeled as a two state, discrete-time Markov chain, that is ch aracterized by two parameters. The steady-state average number of tran sitions on a signal is expressed as a function of the Markov chain par ameters. Formulas for the two parameters associated with the gate outp ut as a function of the corresponding parameters associated with the g ate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits withou t reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconverg ent fanout, the estimation procedure is based on the (local) use of OB BDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of recon vergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.