LOW-POWER VLSI DESIGN TECHNIQUES - THE CURRENT STATE

Increasing demand for portable electronics for computing and communica tion, as well as other applications, has necessitated longer battery l ife, lower weight, and lower power consumption. In order to satisfy th ese requirements, research activities focusing on low power/low voltag e design techniques are underway. Since 'power' is now one of the desi gn decision variables, the expanded design space required for low powe r has further increased the complexity of an already non-trivial task. Low power design basically involves two concomitant tasks: power esti mation and analysis and power minimization. These tasks need to be car ried out at each of the levels in the design hierarchy, namely, the be havioral, architectural, logic, circuit and physical levels. In this s urvey of the current state of the field, many of the salient power est imation and minimization techniques proposed for low power VLSI design are reviewed. For each of the design levels, we provide an overview o f several power estimation and minimization approaches and the CAD too ls that support them. Finally, future research issues are discussed th at will be necessary in order to make the low power design endeavor a successful one.