DESIGN OF HIGH-PERFORMANCE DIGITAL HEARING-AID PROCESSOR

Authors
PARK YC KIM DW KIM IY
Citation
Yc. Park et al., DESIGN OF HIGH-PERFORMANCE DIGITAL HEARING-AID PROCESSOR, Electronics Letters, 34(17), 1998, pp. 1631-1632
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
34
Issue
17
Year of publication
1998
Pages
1631 - 1632
Database
ISI
SICI code
0013-5194(1998)34:17<1631:DOHDHP>2.0.ZU;2-S
Abstract
A digital hearing aid processor (DHAP) chip built around a general-pur pose 16 bit DSP core is presented. The designed DHAP performs a nonlin ear loudness correction of eight frequency bands based on acoustic mea surements. The DHAP provides all the flexibility needed to implement a udiological algorithms. Ln addition, the chip has a low power feature and 5,500 x 5,000 mu m(2) dimensions that make it suitable for wearabl e hearing aids.