QUANTIZED CONDUCTANCE IN A SMALL ONE-DIMENSIONAL SI WIRE ON A THIN SILICON-ON-INSULATOR SUBSTRATE FABRICATED USING SIN-FILM-MASKED OXIDATION

A new fabrication technique for a one-dimensional (1D) Si wire on a se paration-by-implanted-oxygen (SIMOX) substrate, which is effective in reducing the parasitic resistance caused by the thin lead Si regions, is proposed. Thermal oxidation of the Si layer on which a stacked stru cture of SiO2 and SIN films is formed does not reduce the thickness of the wide two-dimensional (2D) Si layer, though the 1D wire becomes th inner by the oxidation. A MOS-type 1D Si wire fabricated using this te chnique shows a clear step-like conductance as a function of gate volt age. Though the measured conductance step is slightly lower than the t heoretically predicted value, it is much larger than previously report ed values. The inherent conductance of the 1D wire can be extracted fr om the measured overall conductance owing to low parasitic resistance. The first conductance step thus obtained agrees well with the theoret ical value of 4e(2)/h.