EVENT SUPPRESSION BY OPTIMIZING VHDL PROGRAMS

The performance and efficiency of event-driven simulations, such as VH DL and Verilog simulation, depend on the number of events that occur d uring the simulation. In this paper, we classify events into two categ ories, sensitive events and insensitive events, according to the neces sity of simulations, and show classification algorithms for both combi national circuits and sequential circuits. We also implement the optim ization methodology that eliminates unnecessary simulation activity ca used by the insensitive events. VHDL programs can be rewritten by augm enting suppressed sensitivity lists. Experiments show that the optimiz ed VHDL programs run almost two times faster than the original ones.