A DESIGN-FOR-TESTABILITY TECHNIQUE FOR REGISTER-TRANSFER LEVEL CIRCUITS USING CONTROL DATA FLOW EXTRACTION/

In this paper, we present a technique for extracting functional (contr ol/data flow) information from register-transfer level controller/data path circuits, and illustrate its use in design for hierarchical test ability of these circuits. This scheme does not require any additional behavioral information. It identifies a suitable control and data flo w from the register-transfer level circuit, and uses it to test each e mbedded element in the circuit by symbolically justifying its precompu ted test set from the system primary inputs to the element inputs and symbolically propagating the output response to the system primary out puts. When symbolic justification and propagation become difficult, it inserts test multiplexers at suitable points to increase the symbolic controllability and observability of the circuit. These test multiple xers are mostly restricted to off-critical paths. Testability analysis and insertion are completely based on the register-transfer level cir cuit and the functional information automatically extracted from it, a nd are independent of the data path bit width owing to their symbolic nature, Furthermore, the data path test set is obtained as a byproduct of this analysis without any further search, Unlike many other design -for-testability techniques, this scheme makes the combined controller -data path very highly testable. It is general enough to handle contro l-flow-intensive register-transfer level circuits like protocol handle rs as well as data-how intensive circuits like digital filters. It res ults in low area/delay/power overheads, high fault coverage, and very low test generation times (because it is symbolic and independent of b it width). Also, a large part of our system-level test sets can be app lied at speed. Experimental results on many benchmarks show the averag e area, delay, and power overheads for testability to be 3.1, 1.0, and 4.2%, respectively. Over 99% fault coverage is obtained in most cases with two-four orders of magnitude test generation time advantage over an efficient gate-level sequential test pattern generator and one-thr ee orders of magnitude advantage over an efficient gate-level combinat ional test pattern generator (that assumes full scan). In addition, th e test application times obtained for our method are comparable with t hose of gate-level sequential test pattern generators, and up to two o rders of magnitude smaller than designs using full scan.