MULTIPLE-VALUED SIGNED-DIGIT ADDER USING NEGATIVE DIFFERENTIAL-RESISTANCE DEVICES

This paper describes a new signed-digit full adder (SDFA) circuit cons isting of resonant-tunneling diodes (RTDs) and metal-oxide semiconduct or field effect transistors (MOSFETs). The design is primarily based o n a multiple-valued logic literal circuit that utilizes the folded-bac k I-V (also known as negative differential-resistance, NDR) characteri stics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of tw o or more digits is achieved by superimposing the signals of individua l wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, t he circuit can perform addition of two arbitrary size binary numbers i n constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based conv ergence routines to tackle the nonlinear device characteristics of qua ntum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat s uperior to other multivalued redundant arithmetic circuits reported in the literature, The SDFA cell requires only 13 MOS transistors and on e RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current- mode adder consisting of 34 MOS transistors. In order to verify the si mulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit.