TRANSIENT AND STEADY-STATE PERFORMANCE MODELING OF PARALLEL PROCESSORS

Authors
MICKLE MH
Citation
Mh. Mickle, TRANSIENT AND STEADY-STATE PERFORMANCE MODELING OF PARALLEL PROCESSORS, Applied mathematical modelling, 22(7), 1998, pp. 533-543
Citations number
9
Categorie Soggetti
Operatione Research & Management Science",Mathematics,"Operatione Research & Management Science",Mathematics,Mechanics
Journal title
Applied mathematical modelling → ACNP
ISSN journal
0307904X
Volume
22
Issue
7
Year of publication
1998
Pages
533 - 543
Database
ISI
SICI code
0307-904X(1998)22:7<533:TASPMO>2.0.ZU;2-L
Abstract
A mathematical procedure is presented as a design/analysis methodology to model computer performance including; (1) Instruction Set Architec ture (ISA), (2) specific hardware implementations of the ISAs, and (3) any benchmark program in one closed form solution. Examples are given employing three classical 8 bit processors, and a classical benchmark program, for both CISC and RISC type implementations. The formulation provides a complete solution giving both steady-state and transient r esults. (C) 1998 Elsevier Science Inc. All rights reserved.