MINIMUM DRIFT ARCHITECTURES FOR 3-LAYER SCALABLE DTV DECODING

This paper describes new techniques for implementing a low-cost video decoder that can decode an HDTV bitstream and display the signal at lo wer resolutions. Two key algorithms are discusssed: down-conversion an d low-resolution motion compensation, in the proposed scheme, incoming blocks are subject to a down-conversion process within the decoding l oop, hence motion compensation is performed from the down-converted im ages. The filters used for down-conversion are based on the concept of frequency synthesis, and the filters used to perform the low-resoluti on motion compensation are determined by an optimal least squares solu tion. Using these algorithms, three different architectures that provi de equal quality with varying system level complexity are presented; t he first is directly derived from the initial model of low-resolution decoder, another attempts to reduce the amount of compuation for the I DCT, while another addresses the concerns regarding the amount of inte rface with an existing decoder structure. All of the above systems are hierarchical with regard to the logic used for filtering and scalable in the amount of memory which is required to reconstruct each output layer. Our simulation results demonstrate that high quality video can be provided at lower-resolutions with significant memory savings.