VLSI IMPLEMENTATION OF THE MOTION ESTIMATOR WITH 2-DIMENSIONAL DATA-REUSE

This paper describes the VLSI implementation with two-dimensional (2-D ) data-reuse architecture for full-search block-matching algorithm. Ba sed on a one-dimensional processing element (PE) array and two data-in terlacing shift-register arrays, the proposed VLSI architecture can ef ficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high thr oughput rate. In addition, the same chips can be cascaded for differen t block sizes, search ranges, and pixel rates.