AN ASIC IMPLEMENTATION OF AN OPTIMIZED DIGITAL VIDEO ENCODER

This paper presents a design of an optimized video encoder using a sim ple pipelined architecture. The proposed video encoder accepts convent ional NTSC/PAL video signals. It also processes the PALplus video sign al using an improved decimation process. The proposed encoder requires only 25K gates, which is a 41% reduction in hardware compared with th e systolic pipelined architecture in [5]. The encoder has been designe d in a 5-stage pipelined structure to assure stable operation. The ove rall performance of the encoder has been verified by using 0.65um CMOS gatearray technology. The chip size is 5170um * 4350um.