NEW DYNAMIC FLIP-FLOPS FOR HIGH-SPEED DUAL-MODULUS PRESCALER

A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D hip-hops is introduced and analyzed . The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchro nous counters, A divide-by-128/129 and 64/65 dual-modulus prescaler us ing proposed hip-hops is measured in 0.8 mu m CMOS technology with the operating clock frequency reaching as high as 1.8 GHz.