THE DESIGN AND FABRICATION OF 0.35 MU-M SINGLE-POLYSILICON SELF-ALIGNED BIPOLAR-TRANSISTORS

Two innovative process technologies are introduced to overcome problem s related to the downscaling of single-polysilicon self-aligned bipola r transistors. First, the use of a selective silicon deposition step b efore Ti salicidation of the structure is shown to improve TiSi2 forma tion on narrow As-doped polysilicon emitters. At the same time, the el evation of the extrinsic base regions around the emitter causes a sign ificant reduction of peripheral electron recombination effects. Second .:he implantation of the intrinsic base a large tilt angle (LATIB) is demonstrated to suppress emitter-to-collector punchthrough along the i solation edges. The first 0.35 mu m single-polysilicon self-aligned bi polar transistors fabricated using a 200 mm complementary metal oxide semiconductor (CMOS) derived bipolar process integrating these novel p rocess technologies are described.