TEST-POINT INSERTION - SCAN PATHS THROUGH FUNCTIONAL LOGIC

Conventional scan design imposes considerable area and delay overheads . To establish a scan chain in the test mode, multiplexers at the inpu ts of flip-flops and scan wires are added to the actual design. We pro pose a low-overhead scan design methodology that employs a new test-po int insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability a nd observability of the selected signals, the test points are used her e to establish scan paths through the functional logic. The proposed t echnique reuses the functional logic for scan operations; as a result, the design-for-testability overhead on area or timing can be minimize d. We show an algorithm that uses the new test-point insertion techniq ue to reduce the area overhead for the full-scan design. We also discu ss its application to the timing-driven partial-scan design.