A PARALLEL-VECTOR CONCURRENT-FAULT SIMULATOR AND GENERATION OF SINGLE-INPUT-CHANGE TESTS FOR PATH-DELAY FAULTS

A new simulation-based method use's single-input change (SIC) vectors to derive tests efficiently for singly testable (ST) path-delay faults (PDF's). A PDF is ST iff there exists a delay test that guarantees it s detection when it is the only PDF in the circuit. It is known that a n ST PDF must have a single-input change test. We utilize this result and present a fault simulator that is specifically tuned to simulate s ingle-input change vectors efficiently. We assign random values to all inputs, and then propagate rising and falling transitions from each i nput while all other inputs are held steady. We present a 16-valued al gebra with which rising and falling PDF's from all inputs are concurre ntly simulated. Using a suitable encoding for signal values, gates are evaluated directly through Boolean operations, and all computation st ages use machine word parallelism. Results on the ISCAS'85 and '89 ben chmarks show that the approach is superior to another published method in terms of both fault coverage and execution time.