A REAL-TIME MPEG2 ENCODING AND DECODING ARCHITECTURE WITH A DUAL-ISSUE RISC PROCESSOR

Integrating a 243 MHz dual-issue RISC processor fore with a small set of dedicated hardware can create a single chip system for real-time en coding and decoding for MPEG2 MP@ML (main profile at main level). A tr ade-off between software and dedicated hardware is very important to d ecide performance of the system. This paper evaluates several MPEG2 en coding and decoding systems, focusing on both chip area and power cons umption. For MPEG2 encoding, a newly introduced hybrid approach includ es the processor core and the dedicated hardware that performs the dis crete cosine transform (DCT), the inverse DCT (IDCT). variable length encoding (VLC) and block loading process. The estimated area for the e ncoder, 23.0 mm(2) using a 0.3-micrometer 1-poly 4-metal CMOS process, is 33% smaller than that of the dedicated hardware approach. The esti mated power consumption fur the encoder is 13% smaller than that of th e dedicated hardware approach. The dual-issue RISC processor approach has the advantage of a small chip area, lots power consumption and tha t of being very easy to program for multimedia applications.