This paper describes a new architecture-based DSP processor, which con
sists of n x n mesh multiprocessor for digital signal processing. A pr
ototype chip, RCDSP9701 has been designed and implemented using a CMOS
0.6 mu m process. This architecture has better performance compare to
the traditional microprocessor solution to Digital Signal Processing.
The proposed method poses remarkable flexibility compare to ASIC (App
lication Specified Integrated Circuits) approach for Digital Signal Pr
ocessing applications. In addition, the proposed architecture is fault
tolerant and suitable for parallel computing applications. In this pa
per, an implementation into a silicon chip of the new architecture is
presented to give a better understanding of our work.