A 300 MHZ DUAL-PORT PALETTE RAM USING PORT SWAP ARCHITECTURE

This paper proposes a dual port color palette SRAM using a single bit line cell. Since the single bit line cell consists of fewer bit lines and transistors than standard dual port cells. it is able to reduce th e area. However, the cell has had a problem in writing a high level. T he port swap architecture solves the problem without any special mecha nism such as a boot strap. In the architecture, each of two bit lines is assigned to the read/write MPU port and the read only pixel port. r espectively. When writing a low level, the MPU port uses pre-assigned bit line. On the other hand, when writing a high level, the MPU port u ses the bit line assigned to the pixel port by a swap operation. Durin g the swapping, the pixel port continues the read operation by using t he bit line assigned to the MPU port. A color palette using this archi tecture is fabricated with a 0.5 mu m CMOS process technology. The mem ory cell sire reduces by up to 43% compared with standard dual purr ce lls. The color palette is able to supply the pixel data at 300 MHz at the supply voltage of 3.3 V. This speed is enough to support the pract ical highest resolution monitors in the world.