Recently, optical packet switch architectures, composed of devices suc
h as optical switches, fiber delay lines, and passive couplers, have b
een proposed to overcome the electromagnetic interference (EMI), pinou
t and interconnection problems that would be encountered in future lar
ge electronic switch cores. However, attaining the buffer size (buffer
depth) in optical packet switches required in practice is a major pro
blem; in this paper, a new solution is presented. An architectural con
cept is;discussed and justified mathematically that relies on cascadin
g many small switches to form a bigger switch with a larger buffer dep
th. The number of cascaded switches is proportional to the logarithm o
f the buffer depth, providing an economical and feasible hardware solu
tion. Packet loss performance, control and buffer dimensioning are con
sidered. The optical performance is also modeled, demonstrating the fe
asibility of buffer depths of several thousand, as required for bursty
traffic.