ULTRATHIN NITRIDE OXIDE (N/O) GATE DIELECTRICS FOR P(+)-POLYSILICON GATED PMOSFETS PREPARED BY A COMBINED REMOTE PLASMA-ENHANCED CVD THERMAL-OXIDATION PROCESS/

Authors
WU YD LUCOVSKY G
Citation
Yd. Wu et G. Lucovsky, ULTRATHIN NITRIDE OXIDE (N/O) GATE DIELECTRICS FOR P(+)-POLYSILICON GATED PMOSFETS PREPARED BY A COMBINED REMOTE PLASMA-ENHANCED CVD THERMAL-OXIDATION PROCESS/, IEEE electron device letters, 19(10), 1998, pp. 367-369
Citations number
11
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE electron device letters → ACNP
ISSN journal
07413106
Volume
19
Issue
10
Year of publication
1998
Pages
367 - 369
Database
ISI
SICI code
0741-3106(1998)19:10<367:UNO(GD>2.0.ZU;2-#
Abstract
Ultrathin nitride-oxide (N/Q similar to 1.5/2.6 nm) dual layer gate di electrics have been incorporated into PMOSFET's with boron-implanted p olysilicon gates. Bored penetration is effectively suppressed by the t op plasma-deposited nitride layer leading to improved short channel pe rformance as compared to PMOSFET's with oxide dielectrics. In addition , improved interface characteristics. and hot carrier degradation immu nity are also demonstrated for the devices,vith the N/O dual layer gat e dielectrics.