A VERY EFFICIENT STORAGE STRUCTURE FOR DWT AND IDWT FILTERS

In this paper, we present an area-efficient storage and routing struct ure to be used as part of either a DWT or an IDWT filter. Such efficie nt structures are necessary for the single chip implementation of mult idimensional DWT and IDWT filters for processing images and video. Whi le the storage structures described in previously published architectu res were adequate for the 1D DWT/IDWT filter, they do not scale well t o a multidimensional implementation. The storage structure design and implementation described in this paper utilizes a combination of well- known efficient RAM cells with simple control to achieve compact size and scalability. When compared to other alternatives, the structure us es less power. In this paper, we examine the problem of constructing, on a single chip, filters for both the multidimensional Discrete Wavel et Transform (DWT) and the multidimensional Inverse Discrete Wavelet T ransform (IDWT). We will use the following example to illustrate where the difficulty lies in constructing such a chip. Consider a filter th at executes transforms on 2D images at the rate of 30 images per secon d. Furthermore, the size N x N of the images is 1024 x 1024, the lengt h L of the filter is 8, the number of octaves O to be generated is 4, and the arithmetic precision P is 24. In image compression, such a fil ter would be a good candidate for the replacement of the filters prese ntly used to perform the block Discrete Cosine Transform (DCT).