NEW DESIGNS FOR A SIGN DETECTOR AND A RESIDUE TO BINARY CONVERTER

In the paper, two algorithms have been developed. The first one has be en exploited in implementing a residue to binary convertor (R//B) for the moduli set {2k - 1, 2k, 2k + 1}. The new convertor is memoryless, which implies that its upper bound is not limited by a memory size. Fu rthermore, this convertor represents a new significant reduction in bo th the hardware requirements and conversion time. A full conversion cy cle consists of three consecutive additions each of (k + 1) bits. The same implementation can be modified slightly to implement a sign detec tor for the same moduli set. Another algorithm has been developed base d on the mixed radix conversion technique. This algorithm was used to implement a new sign detector. This new detector is very efficient in the sense that it requires only two addition cycles each of (k + 1) bi ts. A further reduction in execution time is possible if pipelining is used. All the circuits presented can be implemented using VLSI techno logy, which gives rise to a reduction in the integrated circuit area.