LOW-POWER COEFFICIENT SEGMENTATION ALGORITHM FOR FIR FILTER IMPLEMENTATION

A new multiplication algorithm is introduced for the low-power impleme ntation of digital filters on CMOS based digital signal processing sys tems. The algorithm decomposes individual coefficients into two less c omplex subcomponents. The decomposition, performed using a heuristic a pproach, divides a given coefficient such that a part is produced whic h can be implemented using a single shift operation, leaving another p art with a reduced wordlength to be applied to the coefficient input o f the hardware multiplier. This results in a significant reduction in the amount of switched capacitance and consequently power consumption. The authors describe the algorithm and present associated results, in cluding the effects of overheads due to shift operations, showing up t o 63% saving in power.