ENHANCING TESTABILITY OF VLSI ARRAYS FOR FAST FOURIER-TRANSFORM

Fast-Fourier-transform (FFT) algorithms are used in various digital si gnal-processing applications, such as linear filtering, correlation an alysis and spectrum analysis. With the advent of very large-scale-inte gration (VLSI) technology, a large collection of processing elements c an be gathered to achieve high-speed computation economically. However , owing to the low pin-count/component-count ratio, the controllabilit y and observability of such circuits decrease significantly. As a resu lt, testing of such highly complex and dense circuits becomes very dif ficult and expensive. M-testability conditions for butterfly-connected and shuffle-connected FFT arrays are proposed. Based on them, a novel design-for-testability approach is presented and applied to the modul e-level systolic FFT arrays. The M-testability conditions guarantee 10 0% single-module-fault testability with a minimum number of test patte rns.