SELF-TESTING APPROACHES FOR VLSI ARRAYS

A self-testing method which is applicable to 1- and 2-dimensional arra ys, is presented. The method is based on a state-table-verification ap proach and a criterion referred to as GI (group identical) testability . GI testability is an extension and modification of PI (partition ide ntical) testability and it is used to simplify response verification f or self-testing. It is shown that the response verifier for PI testabi lity does not always detect all faults and a new response verifier for GI-testable arrays is proposed. CGI-testable arrays which are simulta neously C and GI testable, are analysed. It is proved that a C-testabl e 1-dimensional array with n cells is GI testable if n greater-than-or -equal-to 2T, where T is the least common multiple of the test sequenc es for verifying a cell in the array. Design for testability approache s for unilateral and bilateral arrays are proposed, and similar condit ions are developed for 2-dimensional arrays. Methods for reducing the size of CGI-testable unilateral and bilateral arrays are duscussed.