Cryogenically cooled CMOS

The factors affecting the feasibility of cryogenically cooled CMOS are revi ewed. This approach becomes more attractive as CMOS feature sizes shrink be low 250 nm where chip performance is limited by interconnect characteristic s. The impact of interconnects is demonstrated using a methodology for esti mating interconnect-limited CMOS performance. The cryogenic behavior of nor mal and superconducting interconnects is reviewed. Cooling the best normal interconnect metals such as Al or Cu to 77 K can produce 9x lower resistivi ty. High-temperature superconductors can produce lower resistance at GHz cl ock frequencies, but would be difficult to produce on low dielectric substr ates compatible with silicon technology. Performance doubling has been demo nstrated for CMOS circuits operating at liquid nitrogen temperature. Compar able performance improvements may be expected down to below 100 nm if proce ss technology is adjusted appropriately. In addition, dramatic increases in DRAM storage times result from exponential decreases in subthreshold leaka ge currents. Circuit reliability should increase correspondingly, apart fro m hot-carrier induced degradation. Thermally efficient packages and refrige rators are required fbr cryogenic CMOS. Microchannel heat. exchangers can p roduce thermally efficient cryogenic packages. However, thermodynamic limit s to refrigerator performance may make operation at higher cryogenic temper atures more attractive.