High-performance semistatic TSPC DFF

Reduction of the size and the power consumption of the DFF the component th at has the largest area occupancy in the standard cell, is extremely useful for the reduction of the same characteristics in the entire chip. The prop osed DFF is a semistatic configuration realizing True-Single-Phrase Clockin g (TSPC). In comparison with the conventional circuit, this one is successf ul in reduction of power consumption and in improvement of circuit characte ristics such as noise endurance. Also, even though the number of NMOSs is a lmost twice that of PMOSs, the lateral pitch is less than in the convention al small DFFs fabricated with the 0.25-mu m SIMOX, bulk, and MT-CMOS low th reshold process common layout, by virtue of a layout in which only the NMOS s are multistaged. The standard cell blocks designed with the proposed DFF are fabricated by a 0.25-mu m SIMOX process. The power consumption is compu ted by measurement of the supply current. It is found that the power consum ption is reduced by 23% on average in comparison with circuits using the co nventional DFF. (C) 1999 Scripta Technica.