A modular programmable CMOS analog fuzzy controller chip

We present a highly modular fuzzy inference analog CMOS chip architecture w ith on-chip digital programmability. This chip consists of the interconnect ion of parameterized instances of two different kind of blocks, namely labe l blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrate d through a 16-rule two-input CMOS 1-mu m prototype which features an opera tion speed of 2.5 Mflips (2.5 x 10(6) fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1. 6 mm(2) including the digital control and memory circuitry used for program mability. Because of the architecture modularity the number of inputs and r ules can be increased with any hardly design effort.