AREA AND PERFORMANCE COMPARISON OF PIPELINED RISC PROCESSORS IMPLEMENTING DIFFERENT PRECISE INTERRUPT METHODS

The paper presents a comparative study of circuit area and performance degradation among four pipelined RISC processors using different prec ise interrupt methods. The precise interrupt methods studied in the pa per include in-order completion, reorder buffer, history file and futu re file. The VHDL is used to model five machines at the register trans fer level. The Synopsys design compiler is used to synthesise these ma chines as a netlist of CMOS logic gates, then gate counts are obtained . Based on the model architecture and benchmark programs, it shows tha t the history file method can achieve the highest performance and cons ume less silicon area than the reorder buffer method and the future fi le method.