HYBRID SIGNED-DIGIT LOGARITHMIC NUMBER SYSTEM PROCESSOR

A combination of the signed digit (SD) and the logarithmic number syst em (LNS) for the creation of a hybrid SD/LNS processor is investigated . Appropriate radices were chosen for the SD system by taking into acc ount both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude num bers was developed to enhance the overall design. The hybrid SD/LNS pr ocessor exploits the parallelism that is offered by the SD number syst em to boost the performance of the fast LNS processors, and compares f avourably to conventional LNS processor designs.