BINARY-TREE TIMING SIMULATION WITH CONSIDERATION OF INTERNAL CHARGES

An accurate and efficient block-level timing simulator is described. T he high accuracy is attributed to a sophisticated delay model, which i ncludes an accurate representation of the wave-form, a consistent and meaningful definition of delay, a consideration of waveform slope effe cts at both input and output of a gate, a consideration of the multipl e charging/discharging paths in the circuit, and a consideration of th e various fan-out effect and various cell-size effects. Efficient dela y calculation is accomplished through a logic-level simulator instead of using a transistor-level simulator. To represent the waveform accur ately, the switching delay and slope are defined and calculated with c onsideration of the internal charges. To consider the internal charges when computing the waveform, a merged PN tree is used to represent a CMOS gate. The characteristics of the PN tree are described and the me thods used to evaluate the conducting paths proposed. The relationship between the RC time constant and the slope waveform is investigated. After the conducting paths are obtained, a recursive algorithm can be applied to compute the RC time constant in series-parallel RC networks , followed by switching delay and slope. The results are satisfactory when compared with Spice.