MODELING AND ANALYSIS OF BRIDGING FAULTS IN EMITTER-COUPLED LOGIC (ECL) CIRCUITS

With the recent achievement of lower power and higher densities, bipol ar ECL technology is expected to be used widely in high performance di gital circuits. Recent investigations have revealed that bridging faul ts can be a major failure mode in ICs. The paper presents a detailed a nalysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults between logical units wit hout feedback and logical units with feedback in ECL are presented. An analytical approach is presented for computation of logic levels at E CL outputs under varying unknown bridging resistances. Effects of brid ging faults and bridging resistances on output logic levels in ECL hav e been examined along with their effects on noise immunity.