Fully-differential first-generation switched-current memory cells with
common-mode feedforward were used to implement a 1.5 bit/stage pipeli
ned A/D converter in a standard digital CMOS process. The peak effecti
ve number of bits (ENOB) for input frequencies over 1 MHz is 7.43, and
with a 20 MHz input signal sampled at 3 M sample/s, the measured SFDR
and SNDR are 45.1 and 40.8 dB, respectively.