A ROUTER ARCHITECTURE FOR REAL-TIME COMMUNICATION IN MULTICOMPUTER NETWORKS

Parallel machines have the potential to satisfy the large computationa l demands of real-time applications. These applications require a pred ictable communication network, where time-constrained traffic requires bounds on throughput and latency, while good average performance suff ices for best-effort packets. This paper presents a new router archite cture that tailors low-level routing. switching, arbitration, flow-con trol, and deadlock-avoidance policies to the conflicting demands of ea ch traffic class. The router implements bandwidth regulation and deadl ine-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay and buffer requirements for time-c onstrained traffic while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parall el machines. To limit the cost of servicing time-constrained traffic, the router includes a novel packet scheduler that shares link-scheduli ng logic across the multiple output ports, while masking the effects o f clock rollover on the represention of packet eligibility times and d eadlines. Using the Verilog hardware description language and the Epoc h silicon compiler, we demonstrate that the router design meets the pe rformance goals of both traffic classes in a single-chip solution. Ver ilog simulation experiments on a detailed timing model of the chip sho w how the implementation and performance properties of the packet sche duler scale over a range of architectural parameters.