LOCATION OF STUCK-AT FAULTS AND BRIDGING FAULTS BASED ON CIRCUIT PARTITIONING

We propose a method of fault diagnosis at the chip level that reduces the number of simulations required to locate defect site(s) by logical ly partitioning the circuit into subcircuits. Candidate subcircuits th at potentially contain the defect site(s) are identified and further p artitioned until the defect site is located with the required resoluti on. Both stuck-at faults and nonfeedback bridging faults are considere d as target fault models to represent defects. At the base of the faul t location procedure is a procedure to identify subcircuits that poten tially contain the fault site. This procedure is matched to the fault model being considered, thus allowing the same partitioning scheme to be applied to various fault models. The procedure presented here is ap plicable to combinational and fully scanned sequential circuits. Exper imental results are presented to demonstrate the effectiveness of circ uit partitioning in reducing the number of fault simulations required to locate a fault.