MAPPING OF NEURAL NETWORKS ONTO THE MEMORY-PROCESSOR INTEGRATED ARCHITECTURE

In this paper, an effective memory-processor integrated architecture, called memory-based processor array for artificial neural networks (MP AA), is proposed. The MPAA can be easily integrated into any host syst em via memory interface. Specifically, the MPA system provides an effi cient mechanism for its local memory accesses allowed by row and colum n bases, using hybrid row and column decoding, which is suitable for c omputation models of ANNs such as the accessing and alignment patterns given for matrix-by-vector operations. Mapping algorithms to implemen t the multilayer perceptron with backpropagation learning on the MPAA system are also provided. The proposed algorithms support both neuron and layer level parallelisms which allow the MPAA system to operate th e learning phase as well as the recall phase in the pipelined fashion. Performance evaluation is provided by detailed comparison in terms of two metrics such as the cost and number of computation steps. The res ults show that the performance of the proposed architecture and algori thms is superior to those of the previous approaches, such as one-dime nsional single-instruction multiple data (SIMD) arrays, two-dimensiona l SIMD arrays, systolic ring structures, and hypercube machines. (C) 1 998 Elsevier Science Ltd. All rights reserved.