A NEW BROAD-BAND BUFFER CIRCUIT TECHNIQUE AND ITS APPLICATION TO A 10-GBIT S DECISION CIRCUIT USING PRODUCTION-LEVEL 0.5 MU-M GAAS-MESFETS/

A new broadband buffer circuit technique and its analytical design met hod are proposed for a high-speed decision circuit featuring both a hi gher input sensitivity and a larger phase margin. The buffer circuit c haracteristics are significantly improved by employing a series peakin g source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peak ing inductance successfully enhances the 3-dB bandwidth of the data-in put buffer and the clock buffer by 7 GHz for both, over conventional d ouble-stage source follower SCFL buffers. The proposed circuit techniq ue and design method are applied to a 10-Gbit/s decision circuit by th e use of production-level 0.5 mu m GaAs MESFETs. The fabricated decisi on circuit achieves a data input sensitivity of 43 mV(p-p) and a phase margin of 240 degrees both at 10-Gbit/s: a 230 mV(p-p) smaller input sensitivity and a 35 degrees larger phase margin than those of convent ional non-peaking inductor types.