A 1.0-GHZ SINGLE-ISSUE 64-BIT POWERPC INTEGER PROCESSOR

The organization and circuit design of a 1.0-GHz integer processor bui lt in 0.25-mu m CMOS technology are presented, A microarchitecture emp hasizing parallel computation with a single late select per cycle, str uctured control logic implemented by read-only-memories and programmab le logic arrays, and a delayed reset dynamic circuit style enabling co mplex functions to be implemented in a few levels of logic are among t he key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.