A 480-MHZ RISC MICROPROCESSOR IN A 0.12-MU-M L-EFF CMOS TECHNOLOGY WITH COPPER INTERCONNECTS

This paper describes the performance improvements of a reduced instruc tion set computer (RISC) microprocessor that has migrated from a 2.5-V technology to a 1.8-V technology. The 1.8-V technology implements cop per interconnects and low V-t field-effect transistors in speed-critic al paths and has an L-eff of 0.12 mu m. Global clock latency and skew are improved by using copper wires, and early mode timings are improve d by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85 degrees C, and with a fast process, produced a 480-MHz RISC microprocessor.