A 2.6-GBYTE S MULTIPURPOSE CHIP-TO-CHIP INTERFACE/

Authors
LAU B CHAN YF MONCAYO A HO J ALLEN M SALMON J LIU J MUTHAL M LEE C NGUYEN T HORINE B LEDDIGE M HUANG KJ WEI J YU L TARVER R HSIA Y VU R TSERN E LIAW HJ HUDSON J NGUYEN D DONNELLY K CRISP R
Citation
B. Lau et al., A 2.6-GBYTE S MULTIPURPOSE CHIP-TO-CHIP INTERFACE/, IEEE journal of solid-state circuits, 33(11), 1998, pp. 1617-1626
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
33
Issue
11
Year of publication
1998
Pages
1617 - 1626
Database
ISI
SICI code
0018-9200(1998)33:11<1617:A2SMCI>2.0.ZU;2-X
Abstract
A 2.6-GByte/s megacell that interfaces to single or double byte wide D RAM's or logic chips is implemented using 0.35-0.18-mu m CMOS technolo gies. Special I/O circuits are used to guarantee 800-Mbit/s/pin data r ate. Microwave PC board design methodologies are used to achieve the m aximum possible interconnect bandwidth.