A 1.8-NS ACCESS, 550-MHZ, 4.5-MB CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8 -ns cycle time, and 9.84-mu m(2) memory cells has been developed using 0.25-mu m CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circui ts combined with reset circuits, a sense amplifier with nMOS source Fo llowers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay tim e of the sense amplifier hut also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense ampl ifier after the signal from the memory cell is input into the sense am plifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier a ctivation-pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventiona l margin. These three techniques are especially useful for realizing u ltrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems.