A 5-MHZ, 3.6-MW, 1.4-V SRAM WITH NONBOOSTED, VERTICAL BIPOLAR BIT-LINE CONTACT MEMORY CELL

This paper describes a 256-Kbit SRAM fabricated using a novel bipolar bit-line contact memory cell having a large static noise margin. Verti cal PMP transistors are introduced at the bit-line contact area, which realizes lower operational voltage and a memory-cell area equivalent to a 4-NMOS-type cell. The minimum operating voltage is 1.4 V without using a boosting technique, and the access time is 60 ns at a V-cc of 1.8 V and room temperature. The power dissipation is 3.6 mW at a V-cc of 1.4 V, The operating V-cc range is 1.43.0 V.