64-KBYTE SUM-ADDRESSED-MEMORY CACHE WITH 1.6-NS CYCLE AND 2.6-NS LATENCY

Authors
HEALD R SHIN K REDDY V KAO IF KHAN M LYNCH WL LAUTERBACH G PETOLINO J
Citation
R. Heald et al., 64-KBYTE SUM-ADDRESSED-MEMORY CACHE WITH 1.6-NS CYCLE AND 2.6-NS LATENCY, IEEE journal of solid-state circuits, 33(11), 1998, pp. 1682-1689
Citations number
8
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
33
Issue
11
Year of publication
1998
Pages
1682 - 1689
Database
ISI
SICI code
0018-9200(1998)33:11<1682:6SCW1C>2.0.ZU;2-W
Abstract
Address base-plus-offset summing is merged into the decode structure o f this 64-KByte (512-Kbit), four-way set-associative cache. This addre ss adder avoids time-consuming carry propagation by using an A + B = K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-mu m process. This wave pipeline d RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access.