FULLY PARALLEL 30-MHZ, 2.5-MB CAM

Translation functions in high-speed communications networks such as In ternet protocol and asynchronous transfer mode are requiring larger an d faster lookup tables, Content addressable memories (CAM's) provide b uilt-in hardware lookup capability with high speed and high flexibilit y in address allocation. Previous high-capacity CAM's have been inadeq uate for emerging applications; comparators are time-shared among mult iple bits or multiple words, resulting in serialized operation. Fully parallel architectures represent the best solution for highspeed opera tion, but previous fully parallel CAM's have lacked the capacity requi red for leading-edge networking applications. This paper describes a f ully parallel (single-clock-cycle) CAM chip. The chip uses a 0.35-mu m digital CMOS technology to achieve 2.5 Mb of CAM storage and 30-MHz o perating frequency, Innovative layout techniques are used to achieve t wo-dimensional decoding, a traditional problem with high-capacity CAM' s. Architecture and operation of the chip are described, including a n ovel NAND match architecture, operation-specific: self-timing loops, a nd on-board cascade management circuits. The chip functions at 31 MHz, with a search access time of 26 ns and an average search power dissip ation of 5.2 W at 25 MHz.